MCA-217
Advanced Computer Architecture
Where performance actually comes from — Flynn's classification and parallel models, instruction-level parallelism and pipelining, memory hierarchy, and multiprocessor coherence.
- Semester
- Semester 3
- Credits
- 3
- Scheme
- 3 lectures a week
- Contact hours
- 40 across four units
- Category
- Core Elective - II
What the paper is
Advanced Computer Architecture is the paper about why a processor is fast, and it answers in one word repeated at every scale: parallelism. Between instructions, between threads, between processors, and between memory banks — each unit is the same idea applied at a different granularity.
It is taught from Hwang and Jotwani with Hennessy and Patterson alongside, which means it is quantitative. Speedup, efficiency, Amdahl's law, pipeline throughput and cache hit rates are all computed, and the computations are the exam.
Unit IV is the hardest and the most current: multithreading, memory consistency models, cache coherence with snoopy and directory protocols, and parallel programming models. Cache coherence in particular is the concept that most often turns up in interviews for systems work.
What to concentrate on
- Pipeline hazards are the centre of the paper. Be able to identify structural, data and control hazards in a given instruction sequence, and to say which of forwarding, stalling or reordering fixes each.
- Amdahl's law, speedup and efficiency are quick, certain marks. So is Flynn's classification — know all four categories with an example machine for each.
- For cache coherence, learn one snoopy protocol properly (MESI is the usual choice) rather than skimming several. Being able to walk a state transition on a two-processor example answers the whole topic.
Syllabus, unit by unit
Summarised from the approved scheme. Hours are the contact hours the scheme allots, which is a fair guide to where the marks sit.
Unit I · Parallel computer models and interconnection
10 hours- Evolution of computer architecture, Flynn's classification, system attributes to performance
- Parallel computer models: multiprocessors and multicomputers, multivector and SIMD computers
- Types of parallelism and performance metrics
- Data and resource dependences, dependency analysis, partitioning and scheduling
- Control flow, data flow and demand-driven mechanisms
- Static and dynamic interconnection networks, bus systems, crossbar switch, multiport memory, multistage and combining networks
Unit II · Instruction sets, processors and memory hierarchy
10 hours- Instruction set architecture, CISC and RISC scalar processors, superscalar processors, VLIW architecture
- SIMD architecture — fine-grained and coarse-grained; vector architectures; data-pipelined and systolic array architectures
- Memory hierarchy: inclusion, coherence and locality, memory capacity planning
- Interleaved memory organisation, pipelined memory access, bandwidth and fault tolerance, cache addressing models
Unit III · Pipelining
10 hours- Linear and nonlinear pipeline processors
- Instruction pipeline design and mechanisms, pipeline hazards
- Dynamic instruction scheduling: scoreboarding and Tomasulo's algorithm
- Branch handling techniques
- Arithmetic pipeline design: static and multifunctional arithmetic pipelines
- Superscalar and super pipeline processor design
Unit IV · Multithreading, coherence and parallel programming
10 hours- Principles of multithreading, MIMD architecture, multithreaded architecture, issues and solutions
- Design issues in shared-memory and distributed-memory MIMD architectures, multiple-context processors
- Synchronisation: models of memory consistency, cache coherence, snoopy and directory-based protocols
- Parallel programming models: shared-variable, message-passing, data-parallel, object-oriented, functional and logic models
- Parallel languages and compilers, language features for parallelism, the parallel programming environment and its tools
How it is examined
- Question 1 is compulsory, covers the whole syllabus, and is made of objective or short-answer questions. It carries 12 marks.
- The rest of the paper is four units matching the four above. Each unit sets two questions and you attempt one, so there are four more answers at 12 marks each.
- Examiners are asked to map every question to a course outcome using Bloom's taxonomy, which is why questions are phrased as “apply”, “analyse” or “evaluate” rather than only “explain”.
The pass mark is 40 out of 100 in every paper.
Learning objectives
- Fundamental techniques of high-performance computing
- Studying and evaluating the benefits of design options in computer architecture
- Experience with and understanding of the application of these techniques
Assumed beforehand
- Computer organisation
Paired in the scheme with MCA-265 Lab based on Core Elective II.
Books it is taught from
- TB1Kai Hwang and Naresh Jotwani, “Advanced Computer Architecture: Parallelism, Scalability, Programmability”, Tata McGraw Hill Education, 3rd edition, 2015
- TB2John L. Hennessy and David A. Patterson, “Computer Architecture: A Quantitative Approach”, Morgan Kaufmann / Elsevier, 5th edition, 2013
Notes for MCA-217
Lecture notes, question papers and assignments filed against MCA-217 are in the library. Everything there has been checked by a moderator before it appears, and an account is free — new ones are approved by hand, which is what keeps the shelf clean.